The present invention relates to an automatic gain control circuit which automatically controls the gain of a variable gain circuit in a semiconductor integrated circuit.
Conventionally, an automatic gain control circuit has been used as a constituent element of a transimpedance amplification circuit which simultaneously converts and amplifies a micro-photocurrent into a voltage signal. FIG. 4 shows the arrangement of a transimpedance amplification circuit disclosed in non-patent literature 1 (Kimikazu Sano, et al., “A Wideband Low-distorted ROSA for Video Distribution Service based on FM Conversion Scheme”, ECOC 2007 Proceedings, Vol. 3, pp. 167-168, 2007).
A transimpedance core circuit 1 converts the current signal obtained by a light-receiving element such as a photodiode (not shown) into a voltage signal. An offset compensation circuit 2 compensates for the offset of an output signal from the transimpedance core circuit 1. A variable gain circuit (variable gain amplifier) 3 amplifies an output signal from the transimpedance core circuit 1. The variable gain circuit 3 outputs an output signal to differential output ports OT and OC via an output buffer 4. An automatic gain control circuit 5 controls the gain of the variable gain circuit 3 by generating a gain control signal to match the amplitude of an output signal from the variable gain circuit 3 with a predetermined set output amplitude.
The automatic gain control circuit 5 will be described in detail below. The automatic gain control circuit 5 includes a peak detection circuit 50, an average value detection circuit 51, an output amplitude setting circuit 52, an operational amplifier 53, resistors r51, r52, r53, and r54, and capacitors c51, c52, and c53. The peak detection circuit 50 detects a peak value THo of an output signal from the variable gain circuit 3. The average value detection circuit 51 detects an average value Ave of the output signal from the variable gain circuit 3. The difference between the peak value THo and the average value Ave is a half value (half amplitude) of the output signal from the variable gain circuit 3. A set output half amplitude ASet as a reference is set in the output amplitude setting circuit 52. The output amplitude setting circuit 52 outputs the set output half amplitude ASet between the non-inverting input port and inverting input port of the operational amplifier 53.
The operational amplifier 53 adds, at its input, the output amplitude of the variable gain circuit 3 to the set output half amplitude ASet output from the output amplitude setting circuit 52 as indicated byAve−Tho+ASet  (1)Since the input of the operational amplifier 53 is almost 0 during stable operation because of the high gain characteristics of the operational amplifier itself, the value of mathematical expression (1) becomes almost 0. As a consequence, mathematical expression (2) holds:THo−Ave≈ASet  (2)
That is, the operational amplifier 53 amplifies the difference between the set output half amplitude ASet and the output half amplitude (THo−Ave) of the variable gain circuit 3, and outputs a gain control signal to the variable gain circuit 3 based on the amplification result. With this operation, the operational amplifier 53 controls the gain of the variable gain circuit 3 so as to stabilize the output half amplitude (THo−Ave) of the variable gain circuit 3 at the set output half amplitude ASet.
For example, a Gilbert-cell type variable gain circuit (see non-patent literature 2) is used as the variable gain circuit 3. FIG. 5 shows the arrangement of the Gilbert-cell type variable gain circuit disclosed in literature 2 (P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer (Kunihiro Asada and Yuzuru Nagata: Supervisors of Translation), “Analysis and Design of Analog Integrated Circuits (lower volume))”, Fourth Edition, BAIHUKAN, pp. 263-264, 2003).
This variable gain circuit includes amplitude adjustment transistors Q30 and Q31 constituting an upper differential pair which performs output amplitude adjustment in accordance with gain control signals GCT and GCC input to the bases, amplitude adjustment transistors Q32 and Q33 constituting the upper differential pair, amplification transistors Q34 and Q35 constituting a lower differential pair whose bases are connected to a positive-phase input port HIT and a reverse-phase input port HIC, a current source I30 having one port connected to the emitters of the amplification transistors Q34 and Q35, and the other port receiving a power supply voltage VEE, a collector resistor R30 having one port receiving a power supply voltage VCC, and the one port connected to the collectors of the amplitude adjustment transistors Q30 and Q32, and a collector R31 having one port receiving the power supply voltage VCC, and the other port connected to the collectors of the amplitude adjustment transistors Q31 and Q33. The collector of the amplification transistor Q34 is connected to the emitters of the amplitude adjustment transistors Q30 and Q31. The collector of the amplification transistor Q35 is connected to the emitters of the amplitude adjustment transistors Q32 and Q33.
In the variable gain circuit shown in FIG. 5, a positive-phase input signal and a reverse-phase input signal output from the transimpedance core circuit 1 are respectively input to the positive-phase input port HIT and the reverse-phase input port HIC, the gain control signals GCT and GCC are respectively input to the amplitude adjustment transistors Q30 and Q31, and the gain control signals GCT and GCC are respectively input to the amplitude adjustment transistors Q33 and Q32 constituting the upper differential pair. The node of the collectors of the amplitude adjustment transistors Q31 and Q33 and the collector R31 is connected to a positive-phase output port HOT. The node of the collectors of the amplitude adjustment transistors Q30 and Q32 and the collector resistor R30 is connected to a reverse-phase output port HOC.
The output amplitude value of the variable gain circuit 3 which is controlled by the automatic gain control circuit 5 shown in FIG. 4 so as to be constant sometimes greatly changes. The phenomenon in which the output amplitude value of the variable gain circuit 3 changes with temperature can occur when the output voltage THo of the peak detection circuit 50 in FIG. 4 and the average voltage Ave of the average value detection circuit 51 differ in temperature dependence. This can be understood from mathematical expression (2).
The automatic gain control circuit 5 detects the difference (THo−Ave) between the output voltage THo of the peak detection circuit 50 and the output voltage Ave of the average value detection circuit 51. The automatic gain control circuit 5 also compares the output voltage difference (THo−Ave) with the output voltage ASet of the output amplitude setting circuit 52, and operates to set the difference to 0. In this case, if the output voltage THo of the peak detection circuit 50 and the output voltage Ave of the average value detection circuit 51 differ in temperature dependence, the output voltage difference (THo−Ave) becomes temperature dependent.
Since the output voltage difference (THo−Ave) as one of comparison determination signals used by the automatic gain control circuit 5 to generate gain control signals has temperature dependence, the gain control signal output from the automatic gain control circuit 5 to the variable gain circuit 3 becomes temperature dependent. As a result, an output amplitude value from the variable gain circuit 3 also becomes temperature dependent. As described above, according to the related art, since the output amplitude of the variable gain circuit 3 inevitably has temperature dependence, a large circuit operation margin is set.